Webinar: Designing Switched-Mode Power Supplies in the High di/dt ERA

Dear Friends,

We have an upcoming webinar on the topic “Designing Switched-Mode Power Supplies in the High di/dt ERA” as per below information. We believe that the content presented during the webinar would be of great use to you if you are involved with SMPS/DC-DC Converter designs. If you are not directly involved with these kind of design then help me to pass it along to your friends/colleagues working in this area.

When: 

Thursday, September 6, 2018 10:30 pm, India Time (Mumbai, GMT+05:30)

Thursday, September 6, 2018 10:00 am, Pacific Daylight Time (San Francisco, GMT-07:00)

Thursday, September 6, 2018 12:00 pm, Central Daylight Time (Chicago, GMT-05:00)

Why this webinar is important:
Engineers building switched-mode power supplies into their systems demand lower cost, smaller size, and lighter weight. Dominated by the cost, size, and weight of these three components; heat sink, inductor, and the capacitor. In general, faster-switching speed — high di/dt enables smaller, lighter, and less expensive versions of these components.

However, there’s a challenge.

Traditional workflows don’t work in the high di/dt era because they are blind to the spike voltages induced across layout parasitics; V_spike = L_parasitic * di/dt. In the high di/dt era, it is necessary to add a post-layout analysis step to the workflow between the pre-layout circuit simulation and physical prototyping steps.

This webinar will explain how and why to do post-layout analysis, specifically how to use the ADS Momentum field solver to extract layout parasitics into an EM-based model that you can add to the pre-layout circuit simulation. In this way, the spike voltages can be determined, and (using “What if…” design space exploration) reduced to an acceptable level before sending the layout for fabrication.

Don’t smoke those precious power devices with expensive, time-consuming, non-deterministic board spins: use this “virtual prototype” method instead.

Who should attend:
High di/dt SMPS designers who are concerned about voltage spikes from layout parasitics.

Presenter Information:
Dr. Colin Warwick, Power Electronics Product Manager, Keysight Technologies

Colin Warwick is the product manager for power electronics at Keysight EEsof EDA, where he is focused on design and analysis tools for engineers building high di/dt switched mode power supplies.

Prior to joining Keysight, Colin was with Royal Signals and Radar Establishment in Malvern, England; Bell Labs in Holmdel, NJ; and The MathWorks in Natick, MA.

He completed his bachelor, masters, and doctorate degrees in physics at the University of Oxford, England. He has published over 50 technical articles and holds thirteen patents.

Happy Designing…..!!

Keysight EEsof India Design Forum 2017

It is my pleasure to invite you to attend Keysight EEsof India Design Forum 2017 to be held at Hyderabad, Bangalore and Ahmedabad on 24th Oct, 26th Oct and 28th Oct 2017 respectively.

Seminar is complimentary but early registration is advised to secure your participation.

You can register for the location of your choice: Register Now

Download the detailed e-invite from here: Design Forum 2017 e-invite

Hope to see you at one of the locations….

 

 

mmWave 5G Phased Array and Beamforming System Design

Date: Thursday, September 28, 2017

Time: 1:00 PM ET \ 10:00 AM PT \ 10:30 PM IST

Beamforming phased array systems are becoming essential in 5G and next generation communications, especially in mmWave frequency bands. This webcast introduces advanced modeling and simulation approaches for various beamforming techniques. We will demonstrate phased array system design while using practical phased arrays in working, system-level beamforming scenarios. The webcast includes a live software demo with typical configurations, weightings, and impairments that affect beam-level performance (such as nonlinearities, coupling, and element variations). We then show how to apply the arrays in communications link applications such as Verizon pre-5G system and 3GPP NR

Register Now

Thermal Effects, Power Integrity and Your PCB

Keysight Technologies has scheduled a free 1-hour webcast on Thermal Analysis of the PCB and its impact on Power Integrity performance.

WHY THIS WEBCAST IS IMPORTANT

Did you know that in addition to validating the electrical performance of the power integrity on your PCB, it is also crucial to perform a thermal validation as well? This webcast introduces the thermal aspects of power integrity in your PCB designs and why it is critical to consider them. To better understand a design’s power integrity from the thermal viewpoint, it provides a theoretical background for heat transfer and overview of the thermal analysis technologies. Finally, the webcast demonstrates the importance of performing thermal analysis on PCB designs by showing a practical PCB design example.

Date: 27th July 2017

Time: 01.00pm Eastern Daylight Time (10.30pm India Time)

Register Now

Webinar Recording Available: Solve your SI & PI challenges using Keysight EEsof EDA Tools

Video recording of my webinar on “Solving your SI & PI challenges” scheduled on 6th April 2017 is now available at my YouTube channel now. Look forward for your comments & suggestions……

You can view the recording here:

For more information:

  1. http://www.keysight.com/find/eesof-ads
  2. http://www.keysight.com/find/eesof-ads-sipro
  3. http://www.keysight.com/find/eesof-ads-pipro

Webinar: Solve your Signal & Power Challenges using SIPro & PIPro

I will be conducting this Webinar on 6th April at 11.00am – 12.30pm (IST). Look forward for your participation.


Keysight Technologies is offering free webinar on 6th April 2017, specifically designed for Signal and Power Integrity Engineers trying to accurately model their printed circuit boards (PCBs), a task that is now more challenging given today’s ever increasing data rates. During the webinar, attendees will learn about SIPro (Signal Integrity Professional) and PIPro (Power Integrity Professional) tools from Keysight Technologies.

SIPro and PIPro provide a cohesive workflow within ADS for signal integrity and power integrity applications in high speed digital board design. Specific use cases will be demonstrated, which will reveal the powerful capabilities of SIPro & PIPro.

Topics to be covered:

– Challenges of increasing speeds & complexity

– Why you need a Channel Simulator

– S Parameters for frequency and time domain data mining

– EM simulation for Signal integrity

– Fast parallel bus DDR4 simulations

– How to Analyze 100 GbE – KP PAM4 vs NRZ

– Power Integrity basics

– Power Integrity IR Drop

Location: At Your PC

How to Register:

Send a mail to tm_india@keysight.com or dial toll free number to register: 1800-11-2626

Webinar: Tolerance Analysis for Planar Microwave Circuits

Webinar: Tolerance Analysis for Planar Microwave Circuits on December 3 at 7 a.m. or 10 a.m. PT (India time: 8.30pm or 11.30pm)

Planar filters and antennas offer the tightest integration and lowest total cost in the majority of integrated RF/Microwave systems. However, tolerance variations in materials, processing, enclosure and environment are often not properly analyzed leading to circuit or system designs that either do not consistently meet specs or are unnecessarily over-spec’d and costly. This is because the task of performing exhaustive tolerance analysis can be intimidating and you may not know where to begin. This presentation provides a framework for automating this process and is illustrated with a 29GHz microstrip filter. The resulting downloadable template provides a robust starting point for you to test your designs against suspected sources of variation and determine which ones have the strongest influence. This methodology makes "build vs. buy" and material/process selection more deterministic and efficient.

Who Should Attend:

RF/Microwave circuit and system board level engineers, planar antenna designers, RF/Microwave system engineers, engineering managers

Click here to Register: Register Now

Webinar News

Date: 22nd May 2012

Time: 11am – 12pm (IST, GMT+5.30)

Abstract: GaN devices are gaining rapid popularity for Power Amplifier design applications and one of the reasons is that GaN devices provides more reliability as compared to other competing technologies. During the webinar we shall present a design case study using RFMD GaN device & discuss a step by step procedure to design GaN PAs using ADS 2011. We shall also discuss various Load Pull techniques in detailed manner which is a very important step in designing Power Amplifiers.

Date: 19th June 2012

Topic: EM based designs using Agilent ADS and EMPro 2011

Time: 11am – 12pm (IST, GMT+5.30)

Abstract: EM simulations are inherent part of high frequency design applications. Enhancements made in ADS2011 release makes EM simulations pretty easy so that every RF designer can feel comfortable to use the power and accuracy of EM simulations in their RF designs. Also, fully integrated Finite Element Method (FEM) simulator in ADS2011 is very useful to simulate non-planar structures/assemblies without having the need to leave ADS environment and paves the way to perform Circuit/Planar EM/3D EM co-simulation with great ease. Also for certain type of complicated assemblies ADS and EMPro integration can be used pretty effectively which offer full design inter-operability without indulging into complex and time consuming process of doing file transfer between the tools etc.

During the course of webinar we shall present tips and tricks for successful and accurate EM simulations using Method of Moments and FEM simulators in ADS2011 and also demonstrate ADS-EMPro link for complex 3D structures.

Date: 24th July 2012

Topic: RF System Architecture & Budget Analysis using Agilent SystemVue

Time: 11am – 12pm (IST, GMT+5.30)

Abstract: Accurate RF System Architecture analysis is the first key step towards 1st pass design success for RF Systems. Agilent SystemVue provides all the key features to perform RF Architecture and System Budget analysis with great ease.

During the course of the webinar we shall discuss the key challenges faced by RF system designers and showcase how Agilent SystemVue handles such complicated analysis with great ease of use. We shall also discuss how to perform Digital/DSP and RF system co-simulation and tackle various potential RF & DSP integration issues so that we can troubleshoot them early in design cycle.

To Register: https://agilent-technologies.webex.com/mw0306ld/mywebex/default.do?nomenu=true&siteurl=agilent-technologies&service=6&rnd=0.012961748207907409&main_url=https://agilent-technologies.webex.com/ec0605ld/eventcenter/event/eventAction.do?theAct

Webinar: Practical RF Circuit Designing

Here is the details of upcoming webinar from Agilent Technologies, all interested are invited to attend….

Title: Practical RF Circuit Designing

Time: 11am – 12noon (India Time Zone, GMT+5.30)

Date: 27th March 2012

Abstract: Designing RF circuits is often seen as a challenging task and to make RF circuits meet desired specifications with component tolerances is even more challenging. During the course of Webinar we shall present a practical approach of higher

yield RF circuit design.

How to join: Register Here

Happy Designing…..

Webcast: Moving to Non-Signaling Manufacturing Test for Wireless Devices

Title: Moving to Non-Signaling Manufacturing Test for Wireless Devices

Date: February 23, 2012
Time: 10 AM PT/ 1 PM ET/ 6 PM UTC
Presented by: Agilent Technologies
Presenter: Jim McCord, Product Manager, Agilent Technologies

Webcast Description:

As wireless devices rapidly evolve, more wireless bands and formats are being implemented on chipsets used in smart phones, tablets, and other wireless communication devices. Manufacturers are looking for cost-effective ways to test these complex devices while moving them quickly into volume manufacturing. Non-signaling test is widely accepted as the fastest, most cost-effective technique for testing current and next-generation wireless devices in manufacturing.

This presentation discusses the requirements to effectively implement non-signaling test including:

  • What is non-signaling test?
  • Chipset test capabilities, now and future
  • Required test equipment capabilities
  • Tools and techniques to maximize throughput with minimum effort

Register Here