Webinar: How to Optimize Your SerDes Design During the Pre-layout Phase

How to Optimize Your SerDes Design During the Pre-layout Phase

In the era of receiver equalization, older stackup and controlled impedance line design tools are obsolete because the metrics that output (frequency response) are irrelevant. The metric that matters today is the post-equalization eye opening.

In this webcast we will show you how to optimize the pre-layout design using a PCI Express transmitter, channel, and receiver as an example.

Who should attend:
Signal integrity engineers designing controlled impedance lines for multigigabit SerDes such as PCI Express.

Register Now