Had a wonderful and interesting HSD Seminar-cum-Workshop at Bangalore on 17th July 2018. It was quite an experience to see so many customers staying till the end and enjoying the hands-on session with immense interest.

Congratulations to all the Quiz winners….!!

Pluses:

Wonderful participation & engagement, Customer presenter from WDC, 90% people stayed back till the end, Super smooth execution with 82+ people doing the hands-on lab session at the same time.

Minuses:

Feeling sad for customers to whom we had to say “NO” due to logistics issue & hall capacity but surely will try to accommodate them in future events.

Here are some of the memories from the event…..!!!

If you missed out on this event, look forward for your participation in next event…

Advertisements

Using EM Simulation Queue in ADS

Hello Friends,

We often perform multiple EM simulations during typical design cycle and one need to wait for one EM analysis to finish before launching another simulation which at times results in inefficient use of precious engineering time. With EM simulation queue feature in ADS, designers can sequence all the jobs to be run and Job Manager window performs sequential EM simulations with great ease.

See the below video on my you tube channel to understand it better:

 

Happy Designing….!!!

Via Characterization and Modeling By Z Input Impedance

In high-speed digital channel design, vias are everywhere and are becoming very crucial elements to the channel performance. Especially with the higher data rate requirements in mobile, networking, and data center applications, the effect of vias in a design is very noticeable. Design engineers have traditionally used time domain reflectometry (TDR) as a tool to characterize and optimize via designs, yet the TDR approach comes with shortcomings such as demanding shorter rise-time step signal or larger bandwidth S-parameters, and inaccurate read-out on the via impedance.

Read full article here:

https://www.signalintegrityjournal.com/articles/864-via-characterization-and-modeling-by-z-input-impedance

High Speed Digital Seminar-cum-Workshop at Bangalore – 17th July

Hello All,

It is my pleasure to invite you for the High Speed Digital Seminar-cum-Workshop scheduled on 17th July at Hotel Radisson Blu, Outer Ring Road, Bangalore. It will be an exciting day with in-depth technical contents which will be of great help if you deal with Signal & Power Integrity problems in your designs.

Download the e-invite for the event from here:

Bangalore HSD Seminar

Look forward to see you at the event….

Happy Designing…!!!!!

High Speed Signal Integrity Seminar and Hands-On Workshop

It is my pleasure to invite you to join us for the complimentary High Speed Signal Integrity Seminar and Hands-On workshop scheduled at Chennai, India on 21st Feb 2018 at Residency Towers, T Nagar.

Download the below e-invite for more information on agenda and registration details.

Happy Designing…..!!!

e-Invite: HSD_Workshop_Chennai