It is my pleasure to invite you to join us for the complimentary High Speed Signal Integrity Seminar and Hands-On workshop scheduled at Chennai, India on 21st Feb 2018 at Residency Towers, T Nagar.
Download the below e-invite for more information on agenda and registration details.
As Dave Dunham from Molex Corp. likes to say “When designing high speed serial links beyond 10 GB/s, everything matters“. Part of that everything is accurate modeling of transmission line losses. It is important to model dielectric and conductor loss accurately.
Here is a very useful presentation with speaker notes on the topic of “Practical Modeling of High Speed Channels Based on Datasheet Input” presented by Bert Simonovich, Lamsim Enterprise Inc at EDICON 2017.
Here is the motivation of the methodology proposed:
As my friend Eric Bogatin often likes to say, “Sometimes an OK answer NOW! is better than a good answer late.” As a high-speed signal integrity practitioner and backplane architect, I often have to come up with an answer sooner, rather than later because of the impact to time and cost to my clients. And that’s why I have been motivated over the last few years to research and develop a simple methodology to accurately determine parameters to feed into modern EDA tools .
It is my pleasure to invite you to attend Keysight EEsof India Design Forum 2017 to be held at Hyderabad, Bangalore and Ahmedabad on 24th Oct, 26th Oct and 28th Oct 2017 respectively.
Seminar is complimentary but early registration is advised to secure your participation.
You can register for the location of your choice: Register Now
Download the detailed e-invite from here: Design Forum 2017 e-invite
Hope to see you at one of the locations….
I would be conducting a day-long, hands-on workshop on High Speed Signal Integrity design at Keysight Technologies, Bangalore office. First session is scheduled on 17th August 2017.
This workshop is complimentary but requires prior registration to receive a formal invite.
Pre Layout SI
- Designing VIAs for optimum High Speed performance
- Controlled Impedance Line Design
- Channel Simulation Basics
- High Speed Serial Link Simulation
- Batch Simulation
- IBIS-AMI Simulation
- Eye Optimization
Post Layout SI
- BRD/ODB++ Layout Import in ADS
- Post Layout SI Simulation with SIPro
- Channel Simulation with Post Layout Data
If you are interested to attend the same, you can drop a mail with your complete contact details at “firstname.lastname@example.org” or leave your details in the comment box….
P.S. If we are not able to accommodate you for the 1st session due to capacity limit or you are not able to make it due to other engagements then we will surely accommodate you in one the future sessions which are likely to happen shortly.
I created a simple tutorial on how to import ODB++ file from a 3rd party layout tool into ADS for simulation with SIPro for signal integrity applications.
Don’t forget to leave your useful comments after watching the video….
Video recording of my webinar on “Solving your SI & PI challenges” scheduled on 6th April 2017 is now available at my YouTube channel now. Look forward for your comments & suggestions……
You can view the recording here:
For more information:
I will be conducting this Webinar on 6th April at 11.00am – 12.30pm (IST). Look forward for your participation.
Keysight Technologies is offering free webinar on 6th April 2017, specifically designed for Signal and Power Integrity Engineers trying to accurately model their printed circuit boards (PCBs), a task that is now more challenging given today’s ever increasing data rates. During the webinar, attendees will learn about SIPro (Signal Integrity Professional) and PIPro (Power Integrity Professional) tools from Keysight Technologies.
SIPro and PIPro provide a cohesive workflow within ADS for signal integrity and power integrity applications in high speed digital board design. Specific use cases will be demonstrated, which will reveal the powerful capabilities of SIPro & PIPro.
Topics to be covered:
– Challenges of increasing speeds & complexity
– Why you need a Channel Simulator
– S Parameters for frequency and time domain data mining
– EM simulation for Signal integrity
– Fast parallel bus DDR4 simulations
– How to Analyze 100 GbE – KP PAM4 vs NRZ
– Power Integrity basics
– Power Integrity IR Drop
Location: At Your PC
How to Register:
Send a mail to email@example.com or dial toll free number to register: 1800-11-2626