Had a wonderful and interesting HSD Seminar-cum-Workshop at Bangalore on 17th July 2018. It was quite an experience to see so many customers staying till the end and enjoying the hands-on session with immense interest.
Congratulations to all the Quiz winners….!!
Wonderful participation & engagement, Customer presenter from WDC, 90% people stayed back till the end, Super smooth execution with 82+ people doing the hands-on lab session at the same time.
Feeling sad for customers to whom we had to say “NO” due to logistics issue & hall capacity but surely will try to accommodate them in future events.
Here are some of the memories from the event…..!!!
If you missed out on this event, look forward for your participation in next event…
We often perform multiple EM simulations during typical design cycle and one need to wait for one EM analysis to finish before launching another simulation which at times results in inefficient use of precious engineering time. With EM simulation queue feature in ADS, designers can sequence all the jobs to be run and Job Manager window performs sequential EM simulations with great ease.
See the below video on my you tube channel to understand it better:
In high-speed digital channel design, vias are everywhere and are becoming very crucial elements to the channel performance. Especially with the higher data rate requirements in mobile, networking, and data center applications, the effect of vias in a design is very noticeable. Design engineers have traditionally used time domain reflectometry (TDR) as a tool to characterize and optimize via designs, yet the TDR approach comes with shortcomings such as demanding shorter rise-time step signal or larger bandwidth S-parameters, and inaccurate read-out on the via impedance.
Read full article here:
I created a simple to follow video tutorial on how to import mlm models (usually provided for High Speed Connectors) in ADS in order to use them for S-Parameter, Transient or Channel Simulations for High Speed Digital applications.
Enjoy the video here….
It is my pleasure to invite you to join us for the complimentary High Speed Signal Integrity Seminar and Hands-On workshop scheduled at Chennai, India on 21st Feb 2018 at Residency Towers, T Nagar.
Download the below e-invite for more information on agenda and registration details.
As Dave Dunham from Molex Corp. likes to say “When designing high speed serial links beyond 10 GB/s, everything matters“. Part of that everything is accurate modeling of transmission line losses. It is important to model dielectric and conductor loss accurately.
Here is a very useful presentation with speaker notes on the topic of “Practical Modeling of High Speed Channels Based on Datasheet Input” presented by Bert Simonovich, Lamsim Enterprise Inc at EDICON 2017.
Here is the motivation of the methodology proposed:
As my friend Eric Bogatin often likes to say, “Sometimes an OK answer NOW! is better than a good answer late.” As a high-speed signal integrity practitioner and backplane architect, I often have to come up with an answer sooner, rather than later because of the impact to time and cost to my clients. And that’s why I have been motivated over the last few years to research and develop a simple methodology to accurately determine parameters to feed into modern EDA tools .
It is my pleasure to invite you to attend Keysight EEsof India Design Forum 2017 to be held at Hyderabad, Bangalore and Ahmedabad on 24th Oct, 26th Oct and 28th Oct 2017 respectively.
Seminar is complimentary but early registration is advised to secure your participation.
You can register for the location of your choice: Register Now
Download the detailed e-invite from here: Design Forum 2017 e-invite
Hope to see you at one of the locations….