Workshop on High Speed Signal Integrity

I would be conducting a day-long, hands-on workshop on High Speed Signal Integrity design at Keysight Technologies, Bangalore office. First session is scheduled on 17th August 2017.

This workshop is complimentary but requires prior registration to receive a formal invite.

Workshop Agenda:

Pre Layout SI

  • Designing VIAs for optimum High Speed performance
  • Controlled Impedance Line Design
  • Channel Simulation Basics
  • High Speed Serial Link Simulation
  • Batch Simulation
  • IBIS-AMI Simulation
  • Eye Optimization

Post Layout SI

  • BRD/ODB++ Layout Import in ADS
  • Post Layout SI Simulation with SIPro
  • Channel Simulation with Post Layout Data

If you are interested to attend the same, you can drop a mail with your complete contact details at “anurag_bhargava@keysight.com” or leave your details in the comment box….

Happy Designing…!!!

P.S. If we are not able to accommodate you for the 1st session due to capacity limit or you are not able to make it due to other engagements then we will surely accommodate you in one the future  sessions which are likely to happen shortly.

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