Webinar: Designing Switched-Mode Power Supplies in the High di/dt ERA

Dear Friends,

We have an upcoming webinar on the topic “Designing Switched-Mode Power Supplies in the High di/dt ERA” as per below information. We believe that the content presented during the webinar would be of great use to you if you are involved with SMPS/DC-DC Converter designs. If you are not directly involved with these kind of design then help me to pass it along to your friends/colleagues working in this area.


Thursday, September 6, 2018 10:30 pm, India Time (Mumbai, GMT+05:30)

Thursday, September 6, 2018 10:00 am, Pacific Daylight Time (San Francisco, GMT-07:00)

Thursday, September 6, 2018 12:00 pm, Central Daylight Time (Chicago, GMT-05:00)

Why this webinar is important:
Engineers building switched-mode power supplies into their systems demand lower cost, smaller size, and lighter weight. Dominated by the cost, size, and weight of these three components; heat sink, inductor, and the capacitor. In general, faster-switching speed — high di/dt enables smaller, lighter, and less expensive versions of these components.

However, there’s a challenge.

Traditional workflows don’t work in the high di/dt era because they are blind to the spike voltages induced across layout parasitics; V_spike = L_parasitic * di/dt. In the high di/dt era, it is necessary to add a post-layout analysis step to the workflow between the pre-layout circuit simulation and physical prototyping steps.

This webinar will explain how and why to do post-layout analysis, specifically how to use the ADS Momentum field solver to extract layout parasitics into an EM-based model that you can add to the pre-layout circuit simulation. In this way, the spike voltages can be determined, and (using “What if…” design space exploration) reduced to an acceptable level before sending the layout for fabrication.

Don’t smoke those precious power devices with expensive, time-consuming, non-deterministic board spins: use this “virtual prototype” method instead.

Who should attend:
High di/dt SMPS designers who are concerned about voltage spikes from layout parasitics.

Presenter Information:
Dr. Colin Warwick, Power Electronics Product Manager, Keysight Technologies

Colin Warwick is the product manager for power electronics at Keysight EEsof EDA, where he is focused on design and analysis tools for engineers building high di/dt switched mode power supplies.

Prior to joining Keysight, Colin was with Royal Signals and Radar Establishment in Malvern, England; Bell Labs in Holmdel, NJ; and The MathWorks in Natick, MA.

He completed his bachelor, masters, and doctorate degrees in physics at the University of Oxford, England. He has published over 50 technical articles and holds thirteen patents.

Happy Designing…..!!


FMCW Radar Design Book

Received my personal copy of new FMCW Radar Design book from the author himself.

Thanks Dr. Janakiraman for your kind gesture, remembering my support & acknowledging the same in your book. Your hardwork is truly inspiring….



Book can be ordered online from this link: Order your copy now…!!!

Happy Designing…!!!!



Had a wonderful and interesting HSD Seminar-cum-Workshop at Bangalore on 17th July 2018. It was quite an experience to see so many customers staying till the end and enjoying the hands-on session with immense interest.

Congratulations to all the Quiz winners….!!


Wonderful participation & engagement, Customer presenter from WDC, 90% people stayed back till the end, Super smooth execution with 82+ people doing the hands-on lab session at the same time.


Feeling sad for customers to whom we had to say “NO” due to logistics issue & hall capacity but surely will try to accommodate them in future events.

Here are some of the memories from the event…..!!!

If you missed out on this event, look forward for your participation in next event…

Using EM Simulation Queue in ADS

Hello Friends,

We often perform multiple EM simulations during typical design cycle and one need to wait for one EM analysis to finish before launching another simulation which at times results in inefficient use of precious engineering time. With EM simulation queue feature in ADS, designers can sequence all the jobs to be run and Job Manager window performs sequential EM simulations with great ease.

See the below video on my you tube channel to understand it better:


Happy Designing….!!!

Via Characterization and Modeling By Z Input Impedance

In high-speed digital channel design, vias are everywhere and are becoming very crucial elements to the channel performance. Especially with the higher data rate requirements in mobile, networking, and data center applications, the effect of vias in a design is very noticeable. Design engineers have traditionally used time domain reflectometry (TDR) as a tool to characterize and optimize via designs, yet the TDR approach comes with shortcomings such as demanding shorter rise-time step signal or larger bandwidth S-parameters, and inaccurate read-out on the via impedance.

Read full article here:


High Speed Digital Seminar-cum-Workshop at Bangalore – 17th July

Hello All,

It is my pleasure to invite you for the High Speed Digital Seminar-cum-Workshop scheduled on 17th July at Hotel Radisson Blu, Outer Ring Road, Bangalore. It will be an exciting day with in-depth technical contents which will be of great help if you deal with Signal & Power Integrity problems in your designs.

Download the e-invite for the event from here:

Bangalore HSD Seminar

Look forward to see you at the event….

Happy Designing…!!!!!