I would be conducting a day-long, hands-on workshop on High Speed Signal Integrity design at Keysight Technologies, Bangalore office. First session is scheduled on 17th August 2017.
This workshop is complimentary but requires prior registration to receive a formal invite.
Pre Layout SI
- Designing VIAs for optimum High Speed performance
- Controlled Impedance Line Design
- Channel Simulation Basics
- High Speed Serial Link Simulation
- Batch Simulation
- IBIS-AMI Simulation
- Eye Optimization
Post Layout SI
- BRD/ODB++ Layout Import in ADS
- Post Layout SI Simulation with SIPro
- Channel Simulation with Post Layout Data
If you are interested to attend the same, you can drop a mail with your complete contact details at “email@example.com” or leave your details in the comment box….
P.S. If we are not able to accommodate you for the 1st session due to capacity limit or you are not able to make it due to other engagements then we will surely accommodate you in one the future sessions which are likely to happen shortly.
I created a simple tutorial on how to import ODB++ file from a 3rd party layout tool into ADS for simulation with SIPro for signal integrity applications.
Don’t forget to leave your useful comments after watching the video….
Video recording of my webinar on “Solving your SI & PI challenges” scheduled on 6th April 2017 is now available at my YouTube channel now. Look forward for your comments & suggestions……
You can view the recording here:
For more information:
Eye Diagram analysis is one of the most commonly used analysis during Pre or Post Layout Signal Integrity simulations.
This short tutorial video explains simple to use steps of performing optimization of key Eye diagram parameters such as Eye Height giving lot of freedom to High Speed designers to tweak their designs.
Also, use of marker slider is explained which can significantly simplify the job of plotting eye diagram for each swept variable after we perform Parameter Sweep or Batch simulation on our pre- or post- layout board designs.
Don’t forget to like or leave a comment after watching the video…
Simulating accurate VIA performance is one of the key to perform good multilayer board design for RF/uWave as well as High Speed Digital applications to maintain Signal Integrity.
Over the years designers tend to believe that only full 3D simulators i.e. FEM or FDTD based solvers can offer accurate simulations for multilayer VIA structures and complex 3D simulations are performed which can take up to several hours to simulate VIA structures causing increased turn around and design iterations.
With newer ADS releases it is now possible to simulate multilayer VIA structures accurately and efficiently using Method of Moments (MoM) i.e. ADS Momentum largely due newer algorithms which are incorporated in ADS to handle such geometries very accurately.
Also newer ADS release comes with a very nice utility to draw these multilayer VIAs pretty quickly and efficiently. Attached technical note offers step by step procedure to use the multilayer VIA utility to draw these kind of VIA structures and discusses simulation of multilayer VIA using Momentum & FEM solver which are fully integrated into ADS environment. Comparison of results using Momentum & FEM solvers are also provided.
VIA Simulations using ADS.pdf
This short tutorial video explains typical steps which can be used to perform Jitter analysis and Jitter Separation for High Speed Digital application using Agilent ADS software.