Tutorials in Signal Integrity Webcast Series: Designing to Win in 100G Ethernet


100Gbit Ethernet can be a significant design hurdle with 4 lanes running at 25Gbit/s across electrical interconnects and backplanes. Moving from 10G and 40G to 100G represents a step-change in design barriers, especially for signal integrity.

How does the design engineer know that an optimization made in channel simulation, will translate into an optimal design on the bench? By adhering to a measurement-to-simulation validation methodology, and building confidence in both sim models and test results.

In this webcast, Xilinx application specialist Brandon Jiao, will discuss the approach for designing links from Ultrascale FPGAs with 32Gbps capable transceivers, routed from daughter-cards, through connectors and a backplane. Brandon will explore the tools and practical methods needed to insure the performance of the link design, check for compliance to 802.3bj specs, and discuss how Xilinx supports their customers for design success. At the end of the webcast, you will understand the important aspects of 100G link design, what design workspaces are available to help you leap into 100G designs, and where to find further design support.


Signal integrity engineers


Brandon Jiao, Transceiver Technical Marketing Engineer, Xilinx Inc.

Enroll to view the October 27, 2016 live broadcast


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