Webinar: How to Optimize Your SerDes Design During the Pre-layout Phase

How to Optimize Your SerDes Design During the Pre-layout Phase

In the era of receiver equalization, older stackup and controlled impedance line design tools are obsolete because the metrics that output (frequency response) are irrelevant. The metric that matters today is the post-equalization eye opening.

In this webcast we will show you how to optimize the pre-layout design using a PCI Express transmitter, channel, and receiver as an example.

Who should attend:
Signal integrity engineers designing controlled impedance lines for multigigabit SerDes such as PCI Express.

Register Now

Advertisements

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out / Change )

Twitter picture

You are commenting using your Twitter account. Log Out / Change )

Facebook photo

You are commenting using your Facebook account. Log Out / Change )

Google+ photo

You are commenting using your Google+ account. Log Out / Change )

Connecting to %s