Multilayer VIA simulation using ADS (Momentum & FEM)

Simulating accurate VIA performance is one of the key to perform good multilayer board design for RF/uWave as well as High Speed Digital applications to maintain Signal Integrity.

Over the years designers tend to believe that only full 3D simulators i.e. FEM or FDTD based solvers can offer accurate simulations for multilayer VIA structures and complex 3D simulations are performed which can take up to several hours to simulate VIA structures causing increased turn around and design iterations.

With newer ADS releases it is now possible to simulate multilayer VIA structures accurately and efficiently using Method of Moments (MoM) i.e. ADS Momentum largely due newer algorithms which are incorporated in ADS to handle such geometries very accurately.

Also newer ADS release comes with a very nice utility to draw these multilayer VIAs pretty quickly and efficiently. Attached technical note offers step by step procedure to use the multilayer VIA utility to draw these kind of VIA structures and discusses simulation of multilayer VIA using Momentum & FEM solver which are fully integrated into ADS environment. Comparison of results using Momentum & FEM solvers are also provided.

Happy Designing…..

Anurag

VIA Simulations using ADS.pdf

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4 thoughts on “Multilayer VIA simulation using ADS (Momentum & FEM)

  1. Hi

    The Subject of my Master thesis is a “RF 4 layer pcb design”.

    I have a question regarding ads 2013. What is the best way to Simulate the 4 layer PCB in Layout.

    I would like, that the S parameters as good as possible close to reality.
    Should I difine layer 2 and layer 4 as a finite area. And if yes should I populate this area with GND pins.

    The Stackup of my Sustrate is:
    1-GND
    2-Power
    3-Signal
    4-GND

    Thank you for your help!
    Yours sincerely

    Ala

    Like

    1. Hi Ala, Kindly provide your mail id alongwith Institute name & address and I shall drop you a mail with my comments as those could be quite lengthy to be described here.

      Like

      1. Hi sir, I have gone through VIA simulations using ADS. But i’m getting probem in layout itself. It is showing as bus connectivity problem with 3 layers in my 4 layer design. I have inserted a pin but it is connected to top layer itself. can u help me on this issue? please

        Like

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